Re: Apple clone on an FPGA

["mspangler" <mspangler@gemsi.com>]

OK, I'm baffled by this whole thread. How can a collection of NAND
gates with blow-upable inputs act as a general purpose CPU? As a logic
device replacer (MMU/IOU/74ls154 ect) it makes sense. But given you
don't know what instructions are coming in what sequence, and there is
microcode in the CPU that has to execute in a strict time sequence, I'm
baffled.

Is there is nice simple link that explains once over lightly how this
works?

confusedly yours;
Mike


Michael J. Mahon wrote:

>
> I expect that the 6502 implementation on the FPGA
> uses a very minor part of the chips resources.
>
> There is no reason to use a slow, big, expensive,
> separate chip to do what can easily fit in a corner
> of an FPGA.
>
> -michael
>
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