[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: 6502 CPU's Read/Write Question
- Subject: Re: 6502 CPU's Read/Write Question
- From: "Bryan Parkoff" <nospam@nospam.com>
- Date: Sat, 26 Mar 2005 14:54:29 GMT
- Newsgroups: comp.sys.apple2
- Organization: SBC http://yahoo.sbc.com
- References: <sb31e.3544$yq2.2188@newssvr12.news.prodigy.com> <qhy8caexc6.fsf@ruckus.brouhaha.com>
- Xref: g2news1.google.com comp.sys.apple2:9788
Eric,
Okay, how do you know for sure? I am curious.
Bryan Parkoff
"Eric Smith" <eric@brouhaha.com> wrote in message
qhy8caexc6.fsf@ruckus.brouhaha.com">news:qhy8caexc6.fsf@ruckus.brouhaha.com...
> "Bryan Parkoff" <nospam@nospam.com> writes:
>> 6502 CPU has R/W pin. Is it possible that all instructions are
>> always
>> set to read only unless R/W pin is turned on to tell some instructions to
>> set to write only. It uses STA instruction for read first then write.
>>
>> For example:
>> Cycle 1: Address Bus: 1000 Data Bus: 8D -- Read only
>> Cycle 2: Address Bus: 1001 Data Bus: 01 -- Read only
>> Cycle 3: Address Bus: 1002 Data Bus: 20 -- Read only
>> Cycle 4: Address Bus: 2001 Data Bus: C1 -- Read only (Old Data)
>> Cycle 4: Turn on R/W pin -- Read $41 from Accumulator
>> Cycle 4: Address Bus: 2001 Data Bus: 41 (New Data)
>>
>> It is like ASL using RMW. What do you think?
>>
>> Bryan Parkoff
>
> No, cycle 4 can only do a read OR a write, not both.
>
> I'm not sure what you're getting at, but a STA absolute instruction
> works like this:
>
> Address Data
> Cycle Bus R/W Bus
> ----- ------- ----- ----
> 1 1000 read 8D opcode fetch
> 2 1001 read 01 low byte of operand's absolute address
> 3 1002 read 20 high byte of operand's absolute address
> 4 2001 write 41 write data from accumulator
>
>
> STA absolute does not read the target location.