Re: Mockingboard Schematic in GIF form

[mjmahon@aol.com (Michael J. Mahon)]

"a" wrote:

>"Michael J. Mahon" <mjmahon@aol.com> wrote in message
>20040822192357.12124.00003851@mb-m01.aol.com">news:20040822192357.12124.00003851@mb-m01.aol.com...
>> Bill Garber wrote:
>>
>> >"Bill Garber" <willy46pa@comcast DOT net> wrote in message
>> >QPKdnX7iDI_hILrcRVn-iA@comcast.com">news:QPKdnX7iDI_hILrcRVn-iA@comcast.com...
>> >:
>> >: Here is one for you to do. Enjoy!
>> >:
>> >: http://garberstreet.netfirms.com/Mockingboard_Schematic.gif
>> >:
>> >: Feel free to download it. It's linked to the Downloads page.
>> >
>> >A small error was pointed out and was repaired. Thanks Michael.
>>
>> You're welcome, Bill--here are the details as you requested:
>>
>> : One note--the component you show as crystal X1 is actually
>> : a capacitor.  I believe its value is 5pf, which, with the 4.7k
>> : resistor, causes about a 25ns delay in the Phase 0 signal.
>> : (The "K" suffix on the "5" indicates +/-10%.)
>>
>> -michael
>>
>
>Bill and Michael,
>this is a great help.  However, I'm confused over the part of the
>schematic that I'm most interested.
>
>If you take a look at your schematic it appears that the output
>at pin 12 of U5 is directly wired to the input at pin 11 of U5.
>It would seem that this would bypass the middle inverter.
>Also, is it correct to read your schematic as having the +5V
>tied to pin 14 of U5 and it is not directly tied to R1 and R2?
>I read it this way since there is not a dot at the intersection
>just below the +5V flag.
>
>Now, a previous thread "Apple II mistery card..." had the
>following link:
>http://apple2.org.za/gswv/a2zine/Docs/MockingboardSchematic.jpg
>It shows that (like yours) there are three inverters in series with
>a cap straddling the inner one.  But, the arrangement of the resistors
>is a little different.  In this case, it appears that the resistors
>are pullup on either side of the cap.

This is the link I posted earlier.  Presumably, it is what
Bill worked from in making his schematic.  I believe it to
be correct.

I was so fixated on the "X1" problem that I didn't trace out
the rest of Bill's circuit.  (I am accustomed to a "signal flow"
traditional schematic, and had to re-draw both of them to
be sure of what was there.)

You are absolutely correct--Bill's schematic has the inverters
and pullups wired inaccurately.

It is basically a chain of three inverters, with 4.7k pullups
on the first two and 1k on the last (buffer).  There is a 5pf
capacitor between the output of the middle inverter and
its input to "integrate" the pulse and so delay the leading
edge by about 25ns.

Use the .jpg schematic as your reference until Bill gets
his updated.

>I need to admit that I'm an electronics novice.  So, I'm not
>trying to point out errors - just understand and learn before
>I fire up the soldering iron.

You are absolutely correct to do so!

>If you have the time, could you check this other drawing and
>help me clarify the arrangement of this delay circuit.
>
>If you have an actual mocking board, a good close up photo
>of both sides might help too.

I actually went looking for mine the other day to double-check
the schematic, but couldn't locate it in the midst of reorganization
chaos.  ;-(

-michael

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