Re: "Co-Processor" Apple ?

[Jeff Blakeney <CUTjblakeney@sympatico.ca>]

On 07 Aug 2004 02:16:48 GMT, mjmahon@aol.com (Michael J. Mahon) wrote:

>Actually, I currently have the 8 Apple //e boards in the AppleCrate
>plus two I/O-configured Apple //e's.  I just tried a IIgs today, and
>it works fine with the speed set slow--I need to find out how to
>slow it down briefly so it can usually run fast.  (I had hoped that
>a reference to a 5.25" disk controller address would work, but it
>doesn't--have to hit the IIgs hardware manual...)

Michael, in case you haven't already looked it up, the IIgs has a
speed register at $C036.  Here are abbreviated descriptions of what
each bit does taken from the Apple IIgs Hardware Reference Manual,
Second Edition:

    Bit - Description
    ---   ------------------------------------------------------------
     7  - Central processor speed (0 is slow, 1 is fast)
     6  - Power-on status (ROM 3 only; set to 1 when system powered on
          with power switch and not a reboot)
     5  - Reserved
     4  - Shadowig enable (0 only banks $00 and $01 are shadowed, 1
          all banks from $00 to $7F are shadowed)
    3-0 - Disk II motor-on detectors

The description of the last four bits I will quote directly from the
book because I'm sure I'll confuse you if I don't:

"Bit Value Description
---- ----- -------------------------------------------------------
0-3+   1   Disk II motor-on address detectors:  To retain Apple II
           peripheral compatibility, the motor-on detectors
           change the system speed to 1.024 MHz whenever a
           Disk II motor-on address is detected.++  When the disk
           motor-off address is accessed, the system speed
           increases to 2.8 MHz again.  For example, when bit 1 is
           1, the FPI switches to 1.024 MHz when address $C0D9 is
           accessed, and returns to 2.8 MHz following a $C0D8
           access.  (See list of addresses below.)
       0   When this bit is 0, the Disk II motor detectors are
           turned off.
           Bits 0 through 3 detect the following addresses:

           Bit   Slot   Motor on   Motor off
           ---   ----   --------   ---------
           0     4      $C0D9      $C0D8
           1     5      $C0D9      $C0D8
           2     6      $C0E9      $C0E8
           3     7      $C0F9      $C0F8

+  For compatibility with future Apple products, use firmware calls
   only to manipulate bits 0 to 3 of the Speed register.
++ Drives designed for previous Apple II computers will function as
   Apple IIGS peripherals only if the system speed is changed to 1.024
   MHz before disk access is attempted."

It looks like you were trying the bits 0-3 trick but if you just want
to control the speed manually, you just need to read this register,
AND it with $7F and write it back, do what you want, read the register
again and OR it with $80 and write it back again.  This should slow
the processor down during you NadaNet code and keep it running at fast
speed when it isn't.

-- 
 Jeff Blakeney - Dean of the Apple II University in the
                 Apple II Community on Syndicomm.com
 CUT the obvious from my address if you want to e-mail me