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Re: Opcode Instruction Question



Linards Ticmanis <ticmanis@coli.uni-sb.de> wrote:

> Bryan Parkoff wrote:
> >     I understand now.  All 65xxx use only 8-bit for program status (P).  Is
> > it true that Intel x86 have 16-bit for program status, but you said it is
> > only 8-bit?
> >     Is it correct that 68K use 16-bit for program status?
> 
> The length of the operands has nothing to do with the length of the
> status word.

Agreed.

The 68000's Status Register happens to be 16 bits, but half of it can
only be accessed if the CPU is operating in supervisor mode.  For user
mode, the accessible part of SR (namely the Condition Code Register or
CCR) is only 8 bits, though it can be treated as 16 bits for convenience
(the high order 8 bits read as zero).

It is quite common that 8-bit micros (including the 65xxx family) have 8
bit processor status registers, while more complex processors may need a
larger register because they support additional features (such as
multiple interrupt priority levels).

16-bit micros may choose to use a 16-bit status register simply out of
convenience, as it matches their natural word size.

The 8-bit micro we currently use at work is the SGS-Thomson ST9.  Its
fundamental instruction fetch size is 8 bits, but there are several
multi-byte instructions where part of the "opcode" is spread over
several bytes, mixed in with data for the operands.  (The later bits of
the "opcode" typically determine the precise addressing mode among
several similar modes, or the direction of data transfer.)

The ST9 has a traditional 8-bit status register (including the N, Z, V
and C flags), but also has several other registers which contain bits
which might be included in a status register on another processor.  An
example is the current interrupt priority level, which is a three bit
field in the ST9's Central Interrupt Control Register; on the 68000, the
equivalent field is in the Status Register (and is only accessible in
supervisor mode).

-- 
David Empson
dempson@actrix.gen.nz