Re: Applesoft I and II and floating-point performance

[processoroverclocked@33mhz.com (Jon Bettencourt)]

In article <20000515031428.01786.00002501@ng-fl1.aol.com>, mjmahon@aol.com
(Michael J. Mahon) wrote:

> Paul Schlyter replied:
> 
> >...
> >In the 80188 the integer multiply was implemented in
> >hardware instead, resulting in a speedup of a factor of about 3: now
> >it required only some 30 clock cycles.
> 
> If it takes more than 3 cycles for an integer multiply,
> then it's not hardware--it's still microcode.

JSR and RTS are 6 cycles. They are less complex than an integer multiply.
Are you saying a JSR is microcode?

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