Re: 6502, 65816 = RISC ?

["Bruce R. McFarling" <ecbm@cc.newcastle.edu.au>]

wbaguhn@nyx10.cs.du.edu (Will Baguhn) wrote:

>In article <nugundamDw9wxq.GEy@netcom.com>,
>Joseph Lee <nugundam@netcom.com> wrote:

>> I always though it was because the 65xxx series did some
>> preprocessing so that it could pull stuff off the bus in 1 
>> cycle and that could be called pseudo-pipelining in terms 
>> of executing an instruction and do processing to prepare 
>> for the next one.  Of course, it doesn't quite explain 
>> why 1 byte/no memory access instructions take 2 cycles 
>> to execute.

> Sure it does... I haven't looked at a timing sheet recently,
> but I think that it doesn't know what the instruction byte 
> is until the end of the first cycle.  That means that it can't
> start working on it until cycle 2.
>
> So.... if we uniformly subtract 1 fetch cycle per opcode, we
> get instructions running in 1 cycle.  ;)

	All 6502 instructions fetch the instruction in cycle 1, 
interpret it in cycle 2 while fetching the following byte, and 
start executing the instruction in cycle 3, which, depending on 
the instruction, may involve incrementing the instruction register, 
but does not for 1 cycle instructions, so that at the end of a 
1 cycle instruction, the following instruction is fetched again. 
And all instructions that do not require access to the memory bus 
on their last cycle execute the fetch of the first byte of the 
next instruction in the last cycle of execution.  That's why 
JSR RTS or PHA PLA do not have the same cycle count: when the 
stack index is fixed *after* the last memory access, that can be  
pipelined with the fetch of the next instruction, but when the 
last cycle is a memory access, it can't be: the 1 cycle difference 
is the pipelining.
	Conceivably, many of the 1 byte instructions could 
take 1 cycle -- but anything past the single-clock pipelining 
of an internal last execution cycle with the fetch of the next 
instruction value starts to cost transisters.  The 1 cycle 
pipelining is almost free, since the trigger of the next 
instruction fetch has to be built into the address mode anyway.
And since the persistent advantages of the 65C02 is the small 
transistor count that made it an attractive (i.e., relatively 
inexpensive) processor when the AppleI was designed, don't 
look for that to change.

-- 
Virtually,

Bruce R. McFarling, Newcastle, NSW
ecbm@cc.newcastle.edu.au