Re: 6502, 65816 = RISC ?

[philip@io.bocaraton.ibm.com (Philip Stephens)]

Henrik 'Ratte' Gudat writes:

> I'm not sure if somebody mentioned that before, but a 
> RISC is supposed to have instructions of fixed length.
> On the 65x, the length of instructions varies from one
> to 4 bytes. 

  I think it's probably best to say that the 65x family
do have some design features that are now considered
to be part of all modern RISC processors, but that they
aren't RISC processors themselves in the strict sense
of the word.

  Specifically, all 65x processors use an instruction
pipeline that permits partial parallelisation of the
decoding and execution process e.g. an instruction can
be executing while the opcode of the next instruction
is being fetched; while an opcode is being decoded the
first operand byte is being fetched, and so on.  The
end result of all this is that instructions in the
65x family require far less machine cycles to execute
than on, for instance, the x86 family.

  Somebody's comment that the 65x processors are about
4 times faster than the x86 processors is in some 
essense correct; on the basis of machine cycles alone,
the 65x family require significantly less cycles per
instruction because of the internal pipelining feature.
But of course there are many factors involved in
how "fast" a processor runs; clock cycles is only one
of them.

  In most other respects, the 65x family are not RISC:
they don't have a fixed-length instruction set, they
don't have a large set of general purpose registers,
and almost all addressing modes require memory
accesses.