Re: 6502, 65816 = RISC ?

[nathan@visi.com (Nathan Mates)]

In article <4v20n2$17jk@bocanews.bocaraton.ibm.com>,
Philip Stephens <philip@io.bocaraton.ibm.com> wrote:
>  I think it's probably best to say that the 65x family
>do have some design features that are now considered
>to be part of all modern RISC processors, but that they
>aren't RISC processors themselves in the strict sense
>of the word.

   About the only "design feature" that the 65xx family has and the
true RISC chips have in common are simpler instruction sets than the
turgid, bloated, "everything including the kitchen sink" instruction
sets of the 80x86 and other processors. The lack of a whole set of
string, loop, and other instructions does not a chip RISC make.

>Specifically, all 65x processors use an instruction pipeline that
>permits partial parallelisation of the decoding and execution process
>e.g. an instruction can be executing while the opcode of the next
>instruction is being fetched; while an opcode is being decoded the
>first operand byte is being fetched, and so on.  The end result of all
>this is that instructions in the 65x family require far less machine
>cycles to execute than on, for instance, the x86 family.

   For the third time in as many days, it's THE WAY THE PROCESSOR
ACCESSES THE BUS. Not pipelining. Electrically, the 6502 takes 1 (one)
clock cycle to read a byte off the bus. The 8086 takes 4 (four). Thus
for _ANY_ memory access, the 6502 is 4 times faster than an 8086 at
the same clock speed to read that byte. 

   The 8086 has a _way_ better pipeline than the 6502-- it pulls in
instructions, operands, and the like into its pipeline. However,
because of the way it was designed to interface with the bus, it acts
slower overall.

   The 6502 can work on different parts of processing an opcode at
once, but that is not pipelining in the sense that modern RISC
processors (and some CISC, such as the Pentium and similar ilk) use
the term 'pipelining'. To them, pipelining is doing different parts of
_DIFFERENT_ opcodes at once-- reading in the opcode, doing the
operations, copying the results to registers, etc. The 6502 does NOT
do that at all.

   Modern pipelining also introduces quirks such as pipeline stalls,
where parts of the pipeline are held up until the input that they
want is ready. [Usual example is a copy to register, then an add
(or other math op) using that register immediately after it. The
processor cannot work on the math op until the value is in the
register, so the math op just sits around until the register load
is done]. 

   With this, your cycle counts for a given instruction can cary
depending on whether there was a pipeline stall in the middle of the
operation or not. On the 6502, cycle counts are very much fixed
because there is no multiple instruction pipelining, and thus no
chance for a pipeline stall.

>  Somebody's comment that the 65x processors are about
>4 times faster than the x86 processors is in some 
>essense correct; on the basis of machine cycles alone,
>the 65x family require significantly less cycles per
>instruction because of the internal pipelining feature.

   No. See above. I guess I'll have to keep repeating this same
bit of info daily until people learn to read.

Nathan Mates
--
<*> Nathan Mates http://www.visi.com/~nathan/      <*>
# What are the facts? Again and again and again-- what are the _facts_?
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# think-- what are the facts, and to how many decimal places?  -R.A. Heinlein