Re: DMA at 2.8 MHz?

[johnmac@fawlty.towers.oz.au (John MacLean)]

In article <1993May18.122045.9632@desire.wright.edu> avogan@desire.wright.edu writes:
>In article <1993May14.120834.14292@actrix.gen.nz>, dempson@swell.actrix.gen.nz (David Empson) writes:
>> In article <m0ntXWq-00009QC@crash.cts.com> ncp@gnh-cathouse.cts.com (Neal Pitts) writes:
>>> Wait, let me understand this - DMA should be done at 1 MHz because of backward
>>> compatability with the IIe or because it's safer to let DMA happen at 1 MHz? 
>>> If it's for backward compatability, the Rev. D RamFAST only works on the GS
>>> anyway...
>> 
>  Actually you will find that you cannot do DMA above 1Mhz, period.  If it
>were possible I would have done it on the RamFAST.  
>.................[Stuff deleted]
>   Now it is possible to transfer data faster than 1 meg/sec.  You have to 
>get access to the processor environment.  You can either replace the processor
>with a circuit (like the Zip does) or if you have a Zip in place you can
>get access to the processor environment via the expansion header on the card.
>Note that the TWGS is not capable of giving up the processor environment. That
>little header on the TWGS is not an expansion header like they claim.  It is
>actually used to attach a test circuit.  If you use the expansion of the Zip
>you need to pull the RDY signal to the CPU and then bus enable.  This allows
>you to push your address and data onto the bus and transfer data at 2.8
>meg/sec.   Actually 2.6 meg/sec with the refresh.  No big sweat.  
>      Drew
OK, any chance of a special version of the RAMFast for IIGS owners with
a ZIPGS that goes via the ZIPGS expansion slot?
I realise this is a very limited market, but it would be great!
-- 
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