Re: 6502 trashing memory cycles...

[Mark McDougall <markm@vl.com.au>]

Tristan Mumford wrote:

> I may be wrong but it would be easier to
> reimplement a 6502 on an FPGA with the extra circuitry built in to
> tristate the outputs during certain cycles.

A 6502 implemented within an FPGA wouldn't necessarily have the same
behaviour cycle-for-cycle - it need not even be cycle-accurate and could
execute some instructions in less cycles than the 6502.

If you're really interesting in cycle-stealing, then you'd probably
clock the FPGA implementation at a multiple of the bus frequency and
enhance the core to signal to external logic that it can have the next
external bus cycle as soon as possible.

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266