Re: 6502 trashing memory cycles...

[Mark McDougall <markm@vl.com.au>]

bieling@terra.es wrote:

>> Cycle  Address Bus  Data Bus      External Operation  Internal
>> Operation 1       0300           Opcode          Fetch Opcode
>> Finish Previous Operation, 0301 + PC
>> 
>> 2       0301           Discarded Data  Fetch Discarded Data
>> Decode RTS
>> 
>> 3       01FD           Discarded Data  Fetch Discarded Data
>> Increment Stack Pointer to 01FE
>> 
>> 4       01FE           02              Fetch PCL
>> Increment Stack Pointer to 01FF
>> 
>> 5       01FF           01              Fetch PCH
>> 
>> 6       0102           Discarded Data  Put out PC
>> Increment PC by 1 to 0103
>> 
>> 7       0103           Next Opcode     Fetch Next Opcode
>> 
> 
> Yes, memory cycles 2,3 and 6 are useless, wasted. An external circuit
> that knew that could put them to better use : to generate sound, or
> to read from the video frame buffer, or for DMA, or... ?

It's called 'pipeling'. For example memory cycle 2 is not "wasted" - at
this point the opcode has not been decoded and the cpu _has no way_ of
knowing whether or not the next byte in memory is required as an
operand, for example. So the system pipelines the operation by fetching
the next byte in case it is required. If you 'stole' that memory cycle
then you'd slow down every instruction that required more than a single
byte.

How do you propose that an external circuit can 'know' which cycles it
can steal??? Even if you could use the cycles, how could it possibly
'know' that the CPU was fetching, say, RTS rather than data that
corresponded to an RTS opcode? Your logic would require a state machine
similar to the instruction decoding logic within the CPU itself. And
even with all that, it would have to disconnect the CPU from the bus
before the next cycle started.

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266