Re: RFC : SOME IDEAS FOR THE APPLE II FPGA'ers

["Michael J. Mahon" <mjmahon@aol.com>]

Mark McDougall wrote:
> Jorge Chamorro Bieling wrote:
>
> > Dou you think that this can ever run as fast as a hardware
> > "emulation" ?
>
>
> Regardless of the underlying architecture, whether RISC or not, *any* 
> process that requires translation is always going to be slower than a 
> fully optimised, native implementation. Period.

Of course, modern x86 implementations are actually RISC emulations of
the x86 architecture, with lots of x86 specialized instructions...

This probably costs them about a factor of 1.5-2, but not enough to
prevent them from winning the "good enough" performance battle with
native hardware RISC implementations.  Having lots of transistors
changes the game--brute force trumps finesse.

And the 6502 is not really a RISC architecture (though it has some
RISC characteristics if you assume that memory speed and logic speed
are equivalent--which they aren't anymore--even SRAM is slower by a
factor of >10).

> If you're really interested in pushing the limits in terms of speed, you 
> have 2 options:
>
> 1. Implement a native 6502 to run as fast as possible. Of course the 
> core only has to be instruction set compatible, you can redesign the bus 
> architecture whatever way you like.

And there goes Apple peripheral compatibility--I'm out.

> 2. Write an emulator for whatever processor you can clock at ridiculous 
> speeds (much higher than you can clock an FPGA) and hope that you can 
> optimise it enough to outpace option #1. Don't forget you need to 
> emulate all I/O in the system including video, which takes a large chunk 
> out of your headroom.

But not so much that it still doesn't make sense (if you don't need
an Apple peripheral bus)--and complete systems are already integrated
as beautiful laptops, etc.

> To suggest you can emulate a 6502 on a RISC processor core within an 
> FPGA faster than a native optimised 6502 implementation is utterly 
> ludicrous.

Depends on the benchmark, and the level of bus compatibility, and
the degree of 6502-specialization of the RISC core, which is what
I've been saying.

I'm also not inclined to expect anyone's pet 6502 project to be
anywhere near as "optimized" as a commercial RISC core, let alone
as optimized as a modern superscalar, multilevel-cache processor.

You *assume* that bus compatiblity is not necessary--I say that it
might as well be pure emulation on an x86 if that's the case.

You *assume* that I/O is not a factor in system performance--I say
that an Apple II without I/O is not very interesting.

You *assume* that any RISC core used for emulation would be off-the-
shelf--I say that adding hardware maintenance of 6502 flags (for
example) would be simple and quite beneficial to CPU performance.

You *assume* that the number of RISC instructions executed is a critical
factor in performance--I say that each memory access takes several times
as long as a RISC instruction, and that many instructions will be
executed in the latency shadows of the memory accesses.

System performance is a many-splendored thing!  And nothing quantitative
can be said about it in the absence of some postulated benchmark or set
of benchmarks--presumeably of interest to the system users.

I know all about theories of performance, and more than a little about
performance realities.

-michael

Music synthesis for 8-bit Apple II's!
Home page:  http://members.aol.com/MJMahon/

"The wastebasket is our most important design
tool--and it is seriously underused."