Re: Emulating 65C02 in ARM

[Charlie Springer <RAM@regnirps.com>]

On Thu, 25 Aug 2005 23:14:30 -0700, I Do It Wrong wrote
(in article <dryPe.125041$E95.83290@fed1read01>):

> Since the ARM's psr flags (n/z/c/v) match up *so close* to the 6502s, by 
> left shifting your 8-bit values 24 bits before doing arithmetic, you get 
> them for free.  Taking a cursory look at the ARM instruction set, it looks 
> like it could emulate any 6502 instruction in 4-5 instructions (not counting 
> overhead from loading memory and other emulator house keeping).
> 
> Pretty nifty.

The barrel shifter is one cycle and can be combined with most instructions. 
Nice how close the psr flags are isn't it? Rumor always had it the a pair of 
Acorn designer flew out to Western Design to look the the 65C816 as the next 
step for the BBC Micro/Acorn line. That were so disappointed that they 
decided they could do better and laid out the ARM architecture on the plane 
back to London. The BBC used the 6502 so they wanted to keep some backward 
compatibility without compromising the new architecture. Can you imagine 
Intel making such a dramatic departure from 8008?

I think a lookup table driven interpreter could be very efficient and a 
recompiler/reassember should do even better. If it really to four to six 
instructons per 6502 instuction it would be equivalent to a 40 to 60 MHz 
65C02 on a 60 MHz ARM7.

Tale a look at the Phillips 2106 on the right at

http://www.regnirps.com/Apple6502stuff/arm.htm

That little black half inch square has a 60 MHz ARM7, 

MCU: 16/32 bit LPC2106 with 128K Bytes Program Flash, 64K Bytes RAM, RTC, 2x 
UARTs, I2C, SPI, 2x 32bit TIMERS, 7x CCR, 6x PWM, WDT, 5V tolerant I/O, up to 
60MHz operation available for the user program. 

Atmel has some similar with dynamic RAM interface and USB.

Intel has Xscale ARMs at 200 and 400 MHz.

-- Charlie Springer