Re: Test: the cycle

["ict@ccess" <gids.rs@sasktel.net>]

On Feb 17, 8:13 am, Antoine Vignau <antoine.vig...@laposte.net> wrote:
> If there's one softswitch we shouldn't play with, this is CYAREG
> ($C036) on the IIgs. One bit handles shadowing in all RAM banks and
> that should be used with precaution.
>
> Please prefer Vlad's or my code to set the fast/slow mode switch,
> otherwise the behaviour of the IIgs is not guaranteed:
>
> 38 20 1F FE B0 05 A9 80 1C 36 C0 xx xx
>
> SEC
> JSR IDROUTINE ($FE1F)
> BCS notiigs
> LDA #%1000_0000
> TRB CYAREG ($C036)
>
> notiigs:
> xx
> xx


Nooooooo!  Please prefer my code. :)

I agree with you that your way is the right way.

And on a discussion point of view, my understanding was that the goal
was to keep the ACC free.

I don't want to get into the hardware aspect of this discussion of
what happens to the hardware when the bits get changed in this
register.

So as a final note I am making a disclaimer.

Use my way at your own risk!  :)