Re: 65c02 VHDL

[Rubywand <rubywand@swbell.net>]

Jeff Blakeney writes ...
> 
> On Fri, 14 Jan 2000 01:48:24 -0800, "Scott L. Baker"
> <scd@teleport.com> wrote:
> 
> >I have written a 65c02 VHDL model and synthesized it.
> >It fits into an Altera 10k30, but I can generate edif netlist
> >files for a number of different FPGA families.
> 
> I would understand this message a lot more if I knew what VHDL, Altera
> 10k30, edif netlist and FPGA were.  :-)
 ....

     Evidently, Scott has written a model for the 65C02 in VHSIC (very high
speed integrated circuit) Hardware Description Language and tried it out under
computer emulation. The model could be directly implemented using an Altera
10k30 programmable logic array IC.



Rubywand