Re: WDC and the 65C design continues to dominate!

[mikew50@aol.com (MikeW50)]

In message <339d51ca.1461876@news.cl.trw.com>, lemenst@fhsmpt.fh.trw.com
(Tom LeMense) was arguing against the idea that the 65816 was a RISC chip.

While in no way trying to disagree with the conclusions (which I happen to
think are symantic more than meaningfull--what difference does the tag
RISC mean? Compare the chips, not the names!), I have talked with Bill
Mensch (the designer of the 65816) about this, and know some of his
thinking.

>1) it's an accumulator based machine!  While this doesn't rule out the
>idea that the 6502 is RISC, it certainly puts it on shaky ground!

Bill's point is that the 65816 has 256 general purpose registers.  They
can be mixed and matched in 2 ad 4 byte chunks for many purposes. You can
even select the 256 bytes of register space you want from the first 64K of
RAM. The A-X-Y registers are simply a way to manipulate the 256 bytes of
direct page registers.

I don't entirely buy this argument, but direct page does have some
advantages. Many of the advantages are shared with RISC chips.

>2) there are only two "general purpose registers" (X & Y) and they are
>really very general purpose at all when it comes to indexing, and just
>try doing math with them...  RISC machines tend to rely on a large
>number (where large is greater than 2) of regs that can be treated as
>equals, with an orthoganal set of instructions.  

See the above. I agree about the "orthoganal set of instructions" dig,
though.

>3) with the possible exception of branches, each instruction should
>take a constant number of cycles to execute, preferably 1.  

Actually, the 65816 does this rather well. For the most part, the number
of cycles is tied directly to the number of address bus accesses required
for the instruction.

Bill once told me why 1 byte instructions took 2 cycles. I forget the
explanation, but it had to do with address bus accesses.

Mike Westerfield