Re: WDC and the 65C design continues to dominate!

[lemenst@fhsmpt.fh.trw.com (Tom LeMense)]

On 11 Jun 1997 16:07:39 GMT, mikew50@aol.com (MikeW50) wrote:
>In message <339d51ca.1461876@news.cl.trw.com>, lemenst@fhsmpt.fh.trw.com
>(Tom LeMense) was arguing against the idea that the 65816 was a RISC chip.
>
>While in no way trying to disagree with the conclusions (which I happen to
>think are symantic more than meaningfull--what difference does the tag
>RISC mean? Compare the chips, not the names!), I have talked with Bill
>Mensch (the designer of the 65816) about this, and know some of his
>thinking.

I absolutely agree with you about comparing the chips, and not the
names!  I have seen some really nice CISC arch's, and some really poor
RISC arch's, and vice-versa.  I like to ignore the label assigned by
the press/sales department/etc. and apply my own label after I have
considered the architecture.

>>1) it's an accumulator based machine!  While this doesn't rule out the
>>idea that the 6502 is RISC, it certainly puts it on shaky ground!
>
>Bill's point is that the 65816 has 256 general purpose registers.  They
>can be mixed and matched in 2 ad 4 byte chunks for many purposes. You can
>even select the 256 bytes of register space you want from the first 64K of
>RAM. The A-X-Y registers are simply a way to manipulate the 256 bytes of
>direct page registers.
>
>I don't entirely buy this argument, but direct page does have some
>advantages. Many of the advantages are shared with RISC chips.

Ah, but I cannot add two of these registers together directly in the
same number of instructions and number of cycles that I can add, say,
a "direct page register" to A.  This would require two memory fetches,
and one memory store, and really isn't RISC.  These are really just
RAM locations that take a shorter instruction length to access.
That's why I don't buy this argument either.

>>2) there are only two "general purpose registers" (X & Y) and they are
>>really very general purpose at all when it comes to indexing, and just
>>try doing math with them...  RISC machines tend to rely on a large
>>number (where large is greater than 2) of regs that can be treated as
>>equals, with an orthoganal set of instructions.  
>
>See the above. I agree about the "orthoganal set of instructions" dig,
>though.

except that I spelled it wrong: orthogonal.  This, to me, is key in
any architecture, RISC or not.  If the registers are really "general
purpose" then they should be interchangable.  For an excellent
counteraxmple of this, consider the 80x86 and its special treatment of
BX and CX for base indexed addressing and looping, for example.  Two
good examples of rather well implemented register stores are the SPARC
arch. and the PIC, though the latter does have a W register in which
most of the math and logical operations are done.  Again, being
accumulator based doesn't rule out being RISC, but it doesn't help
either -- need more instructions to get from regs to Acc and back.

>>3) with the possible exception of branches, each instruction should
>>take a constant number of cycles to execute, preferably 1.  
>
>Actually, the 65816 does this rather well. For the most part, the number
>of cycles is tied directly to the number of address bus accesses required
>for the instruction.

Yep, which is what I pointed out under the "why the 65x02 is sorta
like a RISC chip" commentary.  I like this part about the 65xx
architecture a lot; the relatively high amount of predictability of
the execution time.  

>Bill once told me why 1 byte instructions took 2 cycles. I forget the
>explanation, but it had to do with address bus accesses.

My assumption was that, since the original 6502 wasn't microcoded, the
control logic was simplified by having a "dummy" bus cycle after any
inherent instruction.  Having to throw away a cycle on a small subset
of instructions seems, at least to me, preferable to making the conrol
logic that much more complex.  If you do remember any other reasons as
to why this is, I'd be interested in hearing them.

-tom