Re: WDC and the 65C design continues to dominate!

[lemenst@fhsmpt.fh.trw.com (Tom LeMense)]

On 2 Jun 1997 17:05:38 GMT, pubpc1@library.ucla.edu wrote:

>Rubywand <rubywand@swbell.net> wrote:
[wdc press release and 65Cxxxx musings deleted]
>
>What about the contention that the 65C02 is the first 8-bit RISC
>chip?  That's what the article claimed.
>
>Before SOMEONE jumps on me and says "don't believe everything you
>read you tone-deaf idiot," let me just say that I don't necessarily
>believe it.  I'm just wondering why some people consider it so.

Good point, Scott.  I have often wondered the same thing myself.  I
have been able to come up with only the following pieces of evidence
to support this assertion:

1) the 6502 (and successors, I assume) is not microprogrammed, rather
it uses hardwired control logic internally, which results in a lower
gate count -- hardwired control and low gate count are two advantages
of RISC.

2) most 6502 instructions take two bus cycles, some of the more CISC'y
ones take more.  Most of the 6502's contemporaries took many more
cycles per instruction, especially processors that used multiphase
system clocks.

I have always rejected the 6502 is RISC claim with the following:

1) it's an accumulator based machine!  While this doesn't rule out the
idea that the 6502 is RISC, it certainly puts it on shaky ground!

2) there are only two "general purpose registers" (X & Y) and they are
really very general purpose at all when it comes to indexing, and just
try doing math with them...  RISC machines tend to rely on a large
number (where large is greater than 2) of regs that can be treated as
equals, with an orthoganal set of instructions.  

3) with the possible exception of branches, each instruction should
take a constant number of cycles to execute, preferably 1.  

4) not that this is a requirement, but RISC machines tend to be
pipelined, due to item #3.

Another, related, claim that I have heard is that people consider the
ARM architecture to be a successor to the 6502.  Now, this one I don't
get at all!  The ARM is truly a RISC architecture, and bears little
(if any) resemblance to the 6502.  If I am missing something here,
please help me out!

As far as the idea that a 65C816 with some minor additions would make
a good 16bit or 32bit micro, let me just remind everyone what
an....interesting...processor the 68HC11 is, which attempts to take a
8 bit core and do 16 bit things with it.  The 65C816 is already
sporting a (poorly) segmented architecture with its 64K bank
addressing capability, which I am sure was done for backward
compatability issues, but just doesn't make for a very tidy
architecture.  Picture trying to get high performance from a 32MB
store divvied up into 64K non-overlapping pages...ick.  Either
implement a segmented memory store correctly, with some form of MMU
and overlapping segments (a la recent intel offerings) or go to a
large linear program store.  In general, the former supports modern
multiuser OS's more readily, while the latter is more appealing to
programmers of single user machines.  

If you take a look at the 6502, and keep in mind all the things that
you like about it, you will probably find that any modern incarnation
of a non-intel architecture is to your liking.  What's so
fundamentally different about a 68000 (for example) from a 6502 (other
than the number of bits and increase in registers)?  Interestingly
enough, the 68K is one of the most CISC'y architectures around.  Now,
from a hardware standpoint, I'd take the 6502 and its bus over that of
the 68K any day, hands down.  The whole asynchronous bit is enough to
drive one nuts...DTACK indeed!  The easy bus interface of the 6502 is
one of the reasons that Woz citied when asked about his choice of
processors.  A 68K or 80x86's system's glue logic alone is enough to
rival the gate count of the entire Apple ][!  

-tom
[who is now out of breath!]