Re: Flame-o-Rama! (was Re: ZipGS 12MHz on

[j0p7771@tam2000.tamu.edu (Jason Perez)]

In article <1994Apr29.053354.1165@labtam.labtam.oz.au>,
Philip Stephens <philip@labtam.oz.au> wrote:
>
>  Now that I think of it, 40 Mhz was being a little optimistic.  But to get
>back to the matter at hand, the 680x0 series requires several clock cycles
>just to fetch a value from memory i.e. it doesn't to my knowledge use any
>pipelining at all.  Hence it effectively runs four times slower at the same

   bzzzt.  that's patently wrong.  the '040 has a six-stage pipeline
for executing instructions.  though a read from main memory can take
several clock cycles and stall the pipe.   a read from the on-chip
cache (which happens about 90% of the time) can be done in one clock
cycle, as fast as reading from one of the registers.  and an instruction
fetch and data fetch can be done at the same time, i.e. has a split cache.

--
Jason Perez                     | "Frodo Lives!"       "Gig 'em!"
j0p7771@tam2000.tamu.edu        | Texas A&M Univ. - it's not just for 
jperez@ee.tamu.edu              |                   farmers anymore!