Re: Flame-o-Rama! (was Re: ZipGS 12MHz on

[jlee@ics.uci.edu (Orion Pax)]

Philip Stephens (philip@labtam.oz.au) wrote:
:   The 65816's pipelining is sufficient to ensure that almost all cycles consumed
: by an instruction are memory cycles.  For example, take the ADC immediate
: instruction: in 8-bit mode, it only consumes 2 cycles, which are the cycles
: required to fetch the instruction!  The instruction decoding takes place
: while the operand is being fetched, and the addition takes place while the
: opcode of the next instruction is fetched.  All other instructions have
: similiar pipelining.

But what about register transfer instructions?  From this info, a tax or
tay should take one cycle, as well as other register transfer instructions.
Does it have something to do with edge-triggered cycles?

Joseph
--
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