Re: digital input at cassette port

[Andy McFadden <fadden@fadden.com>]

jboothbee@gmail.com wrote:
>>Practically, they cannot be sensed faster than once every 4 cycles,
>>so that's the real bandwidth limiter.
> 
> limited by LDA?
> 
> how about with an accelerator?

On a IIgs, change the DP to overlap $c000, and you can do it every 3 cycles.

Whether you'd want to do it at full IIgs speed is a separate question.  I
remember the guys drawing text in the screen border reduced the speed to
1MHz because of timing irregularities (due to DRAM refresh??) at 2.8MHz.

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