Re: A look at the C-One (Commodore One) reconfigurable computer

["Kryten" <kryten_droid_obfusticator@ntlworld.com>]

"MagerValp" <MagerValp@cling.gu.se> wrote in message 
p14ekg0og8l.fsf@panini.cling.gu.se">news:p14ekg0og8l.fsf@panini.cling.gu.se...

> Jeri uses a CPLD (a 3032 iirc) with a state machine to load data from
> rom into the 1k30. Once the 1k30 core is bootstrapped, it takes over
> the boot process.

Hmm, so it has to drive the address lines of a Flash PROM.

I'm a bit short of real estate, I thought I could do this:

- small CPLD puts nop-codes on a (hard) CPU (65C02/Z80) data bus in a 16K 
space.
- and routes the data to the FPGA
- CPU jumps to FPGA boot data and tries to 'run'
- CPU sees nop codes and thus increments address lines through 16K
- FPGA sees 16K of config bytes
- CPU selects next 16K page of config ROM
- Repeats until FPGA loaded

The advantage of this is that the config data sits in the same ROM as used 
for 6502 firmware.

Using a hard CPU like this might avoid the cost of a separate config ROM,
and free valuable FPGA resources.