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Re: A look at the C-One (Commodore One) reconfigurable computer
>>>>> "K" == Kryten <kryten_droid_obfusticator@ntlworld.com> writes:
K> Intriguing. I guess that bit is in one of the non-volatile FPGAs?
Nope, they're both SRAM based.
K> I've been puzzling over the FPGA booting process for my own
K> project. I have a hard 65C02 and Flash ROM already, so I could them
K> to config the FPGA, but then I'd need some RAM and a small CPLD for
K> minimal memory / io decoding. In the end I think I may just use a
K> small AVR to do the job.
Jeri uses a CPLD (a 3032 iirc) with a state machine to load data from
rom into the 1k30. Once the 1k30 core is bootstrapped, it takes over
the boot process.
K> I presume the Daniel Wallner T65 is just a part of the CPC project.
No, the RISC CPU is Tobias' own design, and the Z80/6502 opcode tables
are just RISC instructions.
--
___ . . . . . + . . o
_|___|_ + . + . + . Per Olofsson, arkadspelare
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