Re: //e, //c, //gs Questions

[dempson@actrix.gen.nz (David Empson)]

Mitchell Spector <spec@vax2.concordia.ca> wrote:

> In article supertimer@aol.com (Supertimer) writes...
> 
> >[The Apple II slot bus has...]
> >a transfer limit of 1MB per second.
> 
>     Are you sure about that? That sounds more like the
> peak limit of a DMA SCSI controller when used in a IIgs
> (a IIe only supports a transfer rate of about 500K+/sec,
> and that too is peak.

The slot bus runs at 1.023 MHz, the same as the motherboard.  A card
that uses DMA can theoretically transfer up to 1 MB per second.

The catch: if you do continual DMA cycles for more than about 14 cycles
in a II+ or IIe, you will "starve" the processor and it will lose its
register contents, causing a major crash as soon as the DMA completes.
This is due to the 6502 and 65C02 using dynamic RAM for its registers -
it needs the clock going to keep them from losing their contents, and
DMA stops the clock to the CPU.

The 65816 has static registers, so it doesn't suffer from this problem.
(The same probably applies to a 65802 in the IIe, but I doubt this is
checked for as it is very rare.)

The Apple High-Speed SCSI card firmware detects what machine it is
running on and sets its DMA hardware to the appropriate mode.  On the
IIgs, it can do continous DMA cycles.  On the IIe, it must give the CPU
occasional cycles, but it uses the simple method of interleaving CPU and
DMA cycles, which is easier to implement in the DMA hardware.

If they had used a smarter ASIC design, it would have been possible to
get transfer rates on the IIe approaching those of the IIgs, by doing
several DMA cycles then letting the CPU have one cycle, and repeating as
requried.  Probably not worth the effort for the amount of extra logic
required, since the IIe can't really deal with that much data.

-- 
David Empson
dempson@actrix.gen.nz
Snail mail: P.O. Box 27-103, Wellington, New Zealand