Re: 6502 trashing memory cycles...

["mdj" <mdj.mdj@gmail.com>]

On Mar 6, 12:35 am, "biel...@terra.es" <biel...@terra.es> wrote:
> On 5 mar, 12:41, demp...@actrix.gen.nz (David Empson) wrote:
>
>
>
>
>
> > I'd dispute that "most" instructions have spare memory cycles. It may be
> > that somewhat more than half have a wasted memory access cycle, but the
> > more commonly used ones don't waste cycles.
>
> > For example, all immediate, zero page and absolute instructions don't
> > waste any memory cycles, but indexing does, as do all single byte
> > instructions, which have a minimum of two cycle execution time.
>
> > Typical code patterns would result in "spare" cycles only appearing
> > intermittently. You certainly can't guarantee a minimum number of spare
> > cycles within any particular period of time for arbitrary code
> > execution, which limits the usefulness of stealing these cycles for
> > something else.
>
> > I'm not sure why the 6502 needs to waste a cycle for things like NOP or
> > INX. The 6801 derivative I used at work (Hitachi 6303) managed to
> > execute these in one cycle.
>
> > Lots of code does thinks like LDA immediate, STA somewhere, repeating
> > for further locations. This could easily go on for ten or twenty
> > instructions with no spare cycles.
>
> > --
> > David Empson
>
> David,
>
> I wouldn't be so sure apriori.
> An analysis of a trace of several seconds would probably reveal the
> truth.
> Anyway, in my spare time I sometimes like to think (and write and
> draw) about a design for an Apple II acelerator, zip-chip like, based
> on a WDS 65c02@20Mhz (if at all possible). It makes me feel sick that
> whenever the address seen in the address bus must go to the real
> (slow) apple II, the whole thing has to slow down from 20 to 1 Mhz,
> and waste up to almost 2000ns in the process (when it happens shortly
> after a just-started phase 0 cycle that must be left to pass-by until
> the next slow cycle). For me, this is enough reason to try to discover
> and avoid such memory cycles...

Your accelerator could end up being more complex than the Apple II :-)

In any reasonable accelerator design, when running high speed it hits
high-speed memory, so there's no problem, and it that mode you can
break any cycle timing rule you like.

Of course, insisting on using a 'real' 65c02 in such a design imposes
a number of constraints on the optimisation you speak of, so you'd be
better with programmable logic, where you can optimise it to the point
where the worst case cycle time is 3. Although why you'd do this, and
not just up the clock speed of the accelerator until you reached the
glass ceiling speed I am not sure.

Matt