Re: Zip Chip programming info / disk image?

["RedskullDC" <RDC@oz.org>]

Hi Michael, Rich et. al


"Michael J. Mahon" <mjmahon@aol.com> wrote in message 
au-dnUaP2_UnuabZ4p2dnA@comcast.com">news:au-dnUaP2_UnuabZ4p2dnA@comcast.com...
> David Wilson wrote:
>>>>then maintain slow mode for a heuristically determined
>>>>50-or-so milliseconds after a slow slot /DEVSEL reference.
>>
>>
>>>So the access to the $C600 would tell the
>>>CPU to slow down, and the timing loops that
>>>access the hardware will take a maximum
>>>of ~50ms ?
>>
>>
>> Accessing $C6xx causes /IOSEL #6 to assert. /DEVSEL #6 is $C0Ex and
>> this is what is used to detect when to slow down (after all, once the
>> Apple II is booted the $C6xx code never gets used again). I seem to
>> recall that the IIgs is clever enough to detect when the motor on
>> signal of a 5.25" drive is turned on and only slows down then.
>
> You mean the disk select level, which starts the motor.  (The motor
> is on for a long time after the select level drops.)
>
>> Provided the loops keep accessing the Disk ][ registers the system will
>> remain in slow mode. 50ms after the last access it speeds up again.
>
> Exactly.
>
> In fact, I use (de-select) references to slot 6 to slow a Zip Chip down
> during NadaNet packet sends and receives.  ;-)  The IIgs is somewhat
> harder to control, since re-triggering a "temporary slow mode" is not
> an option--instead, the speed-critical region(s) have to be "bracketed"
> with "slow down" and "speed up" mode changes.

Thanks for the pointers, I found the zip8000 disk on Asimov ok.
the tech.details file is sufficiently detailed to explain the inner 
workings.

Was the schematic diagram in the recently posted zip patent docs
accurate? I noticed it shows a 2716 eprom, which makes me thing this was
for an earlier (later?) expansion card style design of the zip chip?

One thing that doesn't appear to be covered is whether it co-exists
with DMA capable devices?
Does it actually work with DMA devices? If so, I assume it would
invalidate all entries in the tag/cache memories after it sees a DMA
transfer (phase 0 clock input to the zip-chip being held low temporarily?)


I don't have any DMA cards, so this is no big deal to me, but I guess it
could be for those with DMA scsi cards etc. who may like to build one
of these.

It would be reasonably easy to replicate the register set that the
zip-chip uses, but the whole tag ram scheme seems somewhat limiting.

Ideally, I would like to never write to Apple2 main memory at all, only
to addresses within $C000-$CFFF, and even then some of those could
be intercepted (such as a PS/2 keyboard driver, for the PS/2 keyboard
interface haning off the FPGA board.)

The 50ms slow-down timer seems like a good idea to maintain compatibility
with normal apple peripheral cards: disk2 , SSC etc.

Applesoft/Integer/Language Card/Main Mem can all be in a 12ns
SRAM hanging off the FPGA.
Initially, writes to the text/gr/hgr pages would have to go to the main 
board,
until VGA drivers are working, then they can go off to the SRAMS
aswell.

The ZIP-Chip seems best documented, so it is probably easiest to
replicate to allow existing software to function as-is.

Anyone have any better ideas, or feel that other accellerator card
programming schemes are superior to the ZIP-chip?

Cheers,
Red

P.S. I have both a Rom1 and 3 GS. Anyone have any info on
the ZIP-GS, or does it adhere to a similar programming scheme?
(with a 65C816 inside of course).
Well down the track, but there is nothing to actually stop us
creating a 65C832 compatible core, since the docs are on the net :)