Re: GSOS File copy error: System Error ($0040). Thoughts?

[dempson@actrix.gen.nz (David Empson)]

Warren Ernst <wernst@gmail.com> wrote:

> On Sep 30, 10:09 pm, demp...@actrix.gen.nz (David Empson) wrote:
> > Warren Ernst <wer...@gmail.com> wrote:
> > > Anyway, I'm now working under the assumption that I should get more
> > > SIMMs. Can someone report what the specs are for these things? RAM
> > > Speed (mine are 70ns, but would 80's work? 60's?)? Fast Page Mode? 3-
> > > chip or 9-chip? Parity or non Parity?
> >
> > From a posting of mine in 1998:
> >
> > As far as the SIMMs go: parity is irrelevant, the SIMMs must support
> > RAS-before-CAS refresh, and some hybrid types may not work.  The speed
> > should be 120 ns or faster.  The safest bet is to use SIMMs that are
> > known to work in a Mac Plus or SE.
> 
> Thanks for the specs. I'm going to assume that the specs for whatever
> card you used in 1998 are the same for this newer card.

Serves me right for reposting old articles without checking. I got one
detail wrong then: it should be "CAS-before-RAS" refresh.

The basic specifications are for all dynamic RAM used in a IIgs, not
just SIMM cards. Any card which relies on the motherboard FPI/CYA to do
row selection and refresh must support the same standards.

Some cards used their own nonstandard refresh hardware and memory
address decoding, but they were mostly in the early days. Any simple
card which supports 1, 2 or 4 rows, all rows the same size (256 MB or 1
MB), is probably using the motherboard support hardware. Even some eight
row cards (such as the OctoRAM) rely on the motherboard, with one
extension to read a single extra bit of the address bus to allow more
rows (not DMA compatible if eight rows are installed).

The RAM used on some memory cards has access speeds in the order of 150
ns, so 120 ns gives plenty of headroom. If the card has an unusually
long delay for processing some signals, it might need faster RAM.

At 2.8 MHz, a single cycle is 357 ns, and the RAM needs to respond in
somewhat less than half a cycle, which would be about 180 ns less logic
delays.

-- 
David Empson
dempson@actrix.gen.nz